SSTL voltage translator with dynamic biasing
US6803788B2 · kind B2 · utility
3Cited by
4References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2002 |
| Grant date | Oct 12, 2004 |
| Priority date | — |
| Expiry date | Jan 24, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/102
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A SSTL interface voltage translator that uses dynamic biasing to translate an input signal to an output signal is provided. The voltage translator uses a first device that, dependent on a first bias signal, causes the output signal to be pulled down, where the first bias signal is dependent on the input signal. The voltage translator also uses a second device that, dependent on a second bias signal, causes the output signal to be pulled up, where the second bias signal is dependent on the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.