System and method for defining a semiconductor device layout
US6804809B1 · kind B1 · utility
17Cited by
13References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2002 |
| Grant date | Oct 12, 2004 |
| Priority date | — |
| Expiry date | Jan 1, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method to create a layout of a semiconductor device for the purpose of fabricating the semiconductor device involves first providing a plurality of partial-area layout cells and then generating the layout of the semiconductor device by placing the plurality of the partial-area layout cells together. The layout can be conveniently expanded to a desirable size by replicating or repeating certain repeatable cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.