Integration scheme for avoiding plasma damage in MRAM technology
US6806096B1 · kind B1 · utility
110Cited by
4References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2003 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Jun 18, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/00
Abstract
A method of fabricating a magnetic memory device and a magnetic memory device structure. A buffer insulating layer is deposited over the top surface of the conductive hard mask of a magnetic memory cell. The buffer insulating layer is left remaining over the conductive hard mask top surface while the various material layers of the device are patterned and etched. The buffer insulating layer prevents the conductive hard mask top surface from being damaged during plasma-containing processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.