Patent · US Expired

Process for manufacturing a DMOS transistor

US6806131B2 · kind B2 · utility

8Cited by
25References
48Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJun 11, 2002
Grant dateOct 19, 2004
Priority date
Expiry dateJun 11, 2022

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D62/151
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

In a new process of making a DMOS transistor, the doping of the sloping side walls can be set independently from the doping of the floor region in a trench structure. Furthermore, different dopings can be established among the side walls. This is achieved especially by a sequence of implantation doping, etching to form the trench, formation of a scattering oxide protective layer on the side walls, and two-stage perpendicular and tilted final implantation doping. For DMOS transistors, this achieves high breakthrough voltages even with low turn-on resistances, and reduces the space requirement, in particular with regard to driver structures.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.