Method for coding semiconductor permanent store ROM
US6806142B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2003 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Jul 7, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/00
Abstract
A method for manufacturing a ROM device includes a semiconductor substrate having an array of field-effect transistors within a ROM region. A first dielectric layer covers the array and all transistors are initially in an “ON” state. A second dielectric layer covers at least one layer of metal interconnection formed over the first dielectric layer. The bit lines do not overlap the transistor-sources. A coding photoresist layer is formed on the second dielectric layer and is patterned to form a plurality of apertures defining exposure windows exposing underlying field-effect transistors to be coded permanently to an “OFF” state. A code etching back process is implemented using the photoresist layer as a mask to etch the first and second dielectric layers, the sources of the MOSFETs, and a portion of the substrate through the exposure windows to form a deep trench, disconnecting the coded MOSFETs from the source lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.