Process for fabricating a MOS transistor of short gate length and integrated circuit comprising such a transistor
US6806156B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2003 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Jun 4, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Process for fabricating a transistor comprises producing source and drain extension regions, consisting in forming a gate region on a semiconductor substrate and in implanting dopants into the semiconductor substrate on either side of and at a certain distance from the gate of the transistor. The producing of the source and drain extension regions consists in forming an intermediate layer (Cl) on the sidewalls of the gate (GR) and on the surface of the semiconductor substrate. This intermediate layer is formed from a material that is less dense than silicon dioxide. The implantation of dopants (IMP) is carried out through that part of the intermediate layer that is located on the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.