Method for forming low dielectric constant damascene structure while employing a carbon doped silicon oxide capping layer
US6806185B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 2002 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Sep 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76829
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Within a damascene method for forming a patterned conductor layer having formed interposed between its patterns a patterned dielectric layer formed of a comparatively low dielectric constant dielectric material method, there is employed a patterned capping layer formed upon the patterned dielectric layer. The patterned capping layer is formed employing a plasma enhanced chemical vapor deposition (PECVD) method in turn employing an organosilane carbon and silicon source material, a substrate temperature of from about 0 to about 200 degrees centigrade and a radio frequency power of from about 100 to about 1000 watts per square centimeter substrate area. The patterned capping layer provides for attenuated abrasive damage to the dielectric layer incident to the damascene method and is typically partially planarized incident to the damascene method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.