Integrated circuit having SiC layer
US6806501B2 · kind B2 · utility
5Cited by
8References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2003 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Feb 5, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/931
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention is related to an integrated circuit having an SiC etch stop layer fabricated using a method for removal of silicon carbide layers and in particular amorphous SiC of a substrate comprising the steps of: converting at least partly said exposed part of said carbide-silicon layer into an oxide-silicon layer by exposing said carbide-silicon layer to an oxygen containing plasma; and removing said oxide-silicon layer from said substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.