Semiconductor integrated circuit device and fault-detecting method of a semiconductor integrated circuit device
US6806731B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 14, 2002 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | May 14, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor integrated circuit device which shortens the time required for testing a divided logic circuit to reduce test cost and a fault-detecting method therefor. The logic circuit is divided into N logic blocks using N+1 scan paths comprises of scan flip-flops each having selectors for selectively picking up the output signals of storage elements which are fed back to the storage elements. A common scan operation may then be carried out on these logic blocks (Logic 1-to Logic N), and a testing operation may be continuously carried out on the logic blocks. The present invention preferably eliminates the overlaps in conventional scan operations, resulting in a shorter test time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.