Page-erasable flash memory
US6807103B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2003 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | May 15, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a page-erasable FLASH memory including a memory array having a plurality of pages each with floating-gate transistors connected by their gates to word lines, a word line decoder connected to the word lines of the memory, and the application of a positive erase voltage to the source or drain electrodes of all the floating-gate transistors of a sector forming a page to be erased. According to the present invention, the word line decoder includes a unit for applying, when a page is being erased, a negative erase voltage to the gates of the transistors of the page to be erased, while applying a positive inhibit voltage to the gates of the transistors of at least one page that is not to be erased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.