Methods and apparatuses for guaranteed coherency of buffered direct-memory-access data
US6807587B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2000 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Mar 5, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for ensuring data coherency in buffered direct memory access (DMA) data transfers. The DMA controller realizes the last piece of data is being transferred to the write buffer. The DMA controller then sends a “Last Write Data” signal to the external memory access arbitration unit. The external memory access arbitration unit then allows completion of all pending memory operations. If a memory request occurs, a wait line is asserted such that memory operations (i.e., reading from, or writing to, the memory) are prevented for all sources other than the DMA channel associated with the “Last Write Data” signal. The external memory access arbitration unit also grants priority to the DMA channel associated with the “Last Write Data” signal. This effectively flushes the write buffer and completes the buffered DMA data transfer. The external memory access arbitration unit then deasserts any asserted wait lines and memory operations are no longer prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.