Method and apparatus for efficiently generating, storing, and consuming arithmetic flags between producing and consuming macroinstructions when emulating with microinstructions
US6807625B1 · kind B1 · utility
3Cited by
8References
21Claims
0Family size
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Key dates
| Filing date | Feb 18, 2000 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Feb 18, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for efficiently generating arithmetic flags in a computer system. The system includes an eflags register to stored partially computed flags computed by an arithmetic logic unit. The stored partial flags are computed in one cycle. The stored flags are decoded by one of two consuming instructions, PRODF or TBIT, in a second cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.