Rohit Bhatia
30Patents
8h-index
58Co-inventors
78Inventor score
Filing activity: Mar 8, 1993 → Dec 9, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5313413A | Apparatus and method for preventing I/O bandwidth limitations in fast fourier transform processors | Physics | 56 | Expired |
| US7856636B2 | Systems and methods of sharing processing resources in a multi-threading environment | Physics | 27 | Active |
| US7992017B2 | Methods and apparatuses for reducing step loads of processors | Physics | 26 | Active |
| US7421689B2 | Processor-architecture for facilitating a virtual machine monitor | Physics | 15 | Active |
| US9009630B2 | Above-lock notes | Physics | 14 | Active |
| US8479029B2 | Methods and apparatuses for reducing step loads of processors | Physics | 11 | Active |
| US6618803B1 | System and method for finding and validating the most recent advance load for a given checkload | Physics | 10 | Expired |
| US7409524B2 | System and method for responding to TLB misses | Physics | 9 | Expired |
| US7213134B2 | Using thread urgency in determining switch events in a temporal multithreaded processor unit | Physics | 7 | Expired |
| US9069690B2 | Concurrent page table walker control for TLB miss handling | Physics | 6 | Active |
| US8219780B2 | Mitigating context switch cache miss penalty | Physics | 5 | Active |
| US7930539B2 | Computer system resource access control | Physics | 5 | Active |
| US6587940B1 | Local stall/hazard detect in superscalar, pipelined microprocessor to avoid re-read of register file | Physics | 5 | Expired |
| US6745322B1 | Apparatus and method for conditionally flushing a pipeline upon a failure of a test condition | Physics | 4 | Expired |
| US6823434B1 | System and method for resetting and initializing a fully associative array to a known state at power on or through machine specific state | Physics | 3 | Expired |
| US6591360B1 | Local stall/hazard detect in superscalar, pipelined microprocessor | Physics | 3 | Expired |
| US6807625B1 | Method and apparatus for efficiently generating, storing, and consuming arithmetic flags between producing and consuming macroinstructions when emulating with microinstructions | Physics | 3 | Expired |
| US7634508B2 | Processing of duplicate records having master/child relationship with other records | Physics | 2 | Active |
| US9848089B2 | Methods and apparatus to generate an overall performance index | Electricity | 2 | Active |
| US9348766B2 | Balanced P-LRU tree for a “multiple of 3” number of ways cache | Physics | 2 | Active |
| US6910122B1 | Method and apparatus for preserving pipeline data during a pipeline stall and for recovering from the pipeline stall | Physics | 2 | Expired |
| US8886979B2 | Methods and apparatuses for reducing step loads of processors | Physics | 1 | Active |
| US6775752B1 | System and method for efficiently updating a fully associative array | Physics | 1 | Expired |
| US6707831B1 | Mechanism for data forwarding | Physics | 1 | Expired |
| US10956929B2 | Systems and methods for instant generation of human understandable audience insights | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.