System and method for supporting precise exceptions in a data processor having a clustered architecture
US6807628B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2000 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Sep 28, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is disclosed a data processor having a clustered architecture that comprises a plurality of clusters and an interrupt and exception controller. Each of the clusters comprises an instruction execution pipeline having N processing stages. Each of the N processing stages is capable of performing at least one of a plurality of execution steps associated with instructions being executed by the clusters. The interrupt and exception controller operates to (i) detect an exception condition associated with one of the executing instructions, wherein this executing instruction issued at time t0, and (ii) generate an exception in response to the exception condition upon completed execution of earlier ones of the executing instructions, these earlier executing instructions issued at time preceding t0.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.