Decoupling capacitance estimation and insertion flow for ASIC designs
US6807656B1 · kind B1 · utility
16Cited by
9References
27Claims
0Family size
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Key dates
| Filing date | Apr 3, 2003 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Apr 3, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for estimating decoupling capacitance during an ASIC design flow is disclosed. The method includes precharacterizing a set of power grid structures to model their respective noise behaviors, and storing the respective noise behaviors as noise factors in a table. During the ASIC design flow for a current design that includes at least one of the precharacterized power grid structures, the corresponding noise factor from the table is used to calculate decoupling capacitance for the current design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.