Performance of integrated circuit components via a multiple exposure technique
US6807662B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 9, 2002 |
| Grant date | Oct 19, 2004 |
| Priority date | — |
| Expiry date | Jul 9, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/32
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An initial layout of an integrated circuit device is separated into a set of definitions for use in a multiple exposure fabrication process. The separation begins with reading a portion of the initial layout and identifying one or more target features within the initial layout. Further, a first revised layout definition is created for a first mask and a second revised layout definition is created for a second mask. The first revised layout definition includes the target features inside the dark-field content. In addition, in one embodiment, the first revised layout definition includes clear areas around each target feature. The second layout definition includes one or more dark features inside the bright-field content. These dark features, when used in the multiple exposure fabrication process, will overlap the target features. The first and second masks may be binary masks, attenuated phase-shifting masks (PSMs) or a combination of a binary mask and an attenuated PSM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.