Method for forming vertical transistor and trench capacitor
US6808979B1 · kind B1 · utility
50Cited by
10References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2003 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | Aug 13, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0385
Abstract
A method for forming a vertical transistor and a trench capacitor. A semiconductor substrate having a pad stacked layer on the surface and a trench formed therein is provided. A capacitor is formed at the bottom part of the trench and a portion of the upper sidewall of the trench is exposed. A conductive wire is then formed on the capacitor, followed by forming a dielectric layer on the exposed sidewalls of the trench. A trench top dielectric is then formed by liquid phase deposition on the conductive wire. A transistor is then formed on the trench top dielectric, which isolates the transistor from the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.