Method to fabricate high-performance NPN transistors in a BiCMOS process
US6809024B1 · kind B1 · utility
16Cited by
9References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 9, 2003 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | May 9, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A method of forming a quasi-self-aligned heterojunction bipolar transistor (HBT) that exhibits high-performance is provided. The method includes the use of a patterned emitter landing pad stack which serves to improve the alignment for the emitter-opening lithography and as an etch stop layer for the emitter opening etch. The present invention also provides an HBT that includes a raised extrinsic base having monocrystalline regions located beneath the emitter landing pad stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.