Digital level shifter with reduced power dissipation and false transmission blocking
US6809553B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2001 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | Oct 15, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018571
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit including a level shifting device such as a high voltage MOS device which is turned on to make an output transition, and feedback circuitry which responds to the transition to turn off the level shifting device. A circuit including two n-channel devices and two p-channel devices can sense when current greater than a threshold flows through both devices of one channel type to prevent false output transitions due to rapid changes in offset voltage, or both features can be provided. Level shifting devices can also be connected so none of the devices receives its acknowledge signal from the device to which it provides an acknowledge signal to avoid a standoff between two devices. For each device, the feedback circuitry can distinguish acknowledge signals so a device that stops transmitting in response to a signal that was not an acknowledge signal cam be restarted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.