Ferroelectric memory
US6809949B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | May 6, 2002 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | May 6, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric memory including a bit line pair, a drive line parallel to and located between the bit lines, and an associated memory cell. The memory cell includes two capacitors, each capacitor connected to one of said bit lines via a transistor, and each capacitor is also connected to the drive line via a transistor. The gates of all three of the transistors are connected to a word line perpendicular to the bit lines and drive line, so that when the word line is not selected, the capacitors are completely isolated from any disturb. The bit lines may be complementary and the cell a one-bit cell, or the cell may be a two-bit cell. In the latter case, the memory includes a dummy cell identical to the above cell, in which the two dummy capacitors are complementary. A sense amplifier with three bit line inputs compares the cell bit line with a signal derived from the two dummy bit lines. The logic states of the dummy capacitors alternate in each cycle, preventing imprint and fatigue. The bit lines are partitioned into a plurality of second level bit lines, each connected to a top level bit line via a group select transistor. The memory includes a plurality of such cells, divided int…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.