Limiter for refresh signal period in DRAM
US6809980B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2003 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | Mar 11, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a device (10) for outputting a refresh signal for a memory cell of a semiconductor memory device, the device (10) comprising:a receiving device for receiving a variable periodic refresh input signal (14);a comparison device (22) for comparing the period duration of the refresh input signal (14) with at least one predeterminable value;an output device (22) for outputting a refresh output signal (24) in a manner dependent on the result of the comparison in the comparison device (22);the output device (22) being designed in such a way thatif the period duration of the refresh input signal (14) lies above a predeterminable maximum value, a refresh output signal (24) with the predeterminable maximum period duration (T_max) can be output and/orif the period duration of the refresh input signal (14) lies below a predeterminable minimum value, a refresh output signal (24) with a predeterminable minimum period duration (T_min) can be output, and otherwise a refresh output signal (24) can be output whose period duration (T_out) is proportional to the period duration (T_in) of the refresh input signal (14).Furthermore, the invention relates to a method for outputting …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.