Patent · US Expired

Analog multiplier

US6810240B2 · kind B2 · utility

3Cited by

12References

6Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Gunter Donig · Poing, DE
Josef Schmal · Hersbruck, DE

Key dates

Filing date	Feb 5, 2001
Grant date	Oct 26, 2004
Priority date	—
Expiry date	Jul 24, 2022

Classification

Technology area (CPC G)Physics
CPC primaryG06G7/163
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The analog multiplier has a MOS input stage. This makes it possible to increase the linearity range of the multiplier. In a development, a cascode circuit having an additional pair of bipolar transistors is provided, which makes it possible to achieve a higher linearity without increasing the supply voltage. The analog multiplier is particularly suitable as a down-converter in a reception path of a mobile radio system.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.