Electromagnetic disturbance analysis method and apparatus and semiconductor device manufacturing method using the method
US6810340B2 · kind B2 · utility
9Cited by
2References
58Claims
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Key dates
| Filing date | Mar 8, 2002 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | Nov 15, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2855
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An electromagnetic disturbance analysis method for analyzing an external noise to a semiconductor integrated circuit includes an impedance extraction step of extracting impedance information on the power wiring in the target semiconductor integrated circuit or the power wiring in the semiconductor integrated circuit and the external power wiring of the semiconductor integrated circuit, an equivalent circuit creating step of creating an equivalent circuit from the impedance information, and an analysis step of supplying a noise waveform externally and analyzing the influence of the noise on the semiconductor integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.