System and method for estimating power consumption of a circuit thourgh the use of an energy macro table
US6810482B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2001 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | Jan 18, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention facilitates relatively accurate power consumption estimates performed at the register transfer level for scaleable circuits with similar architectural characteristics and features. A power evaluation process of the present invention includes a critical path delay based macro energy model creation process and a scaleable power consumption estimation process. In one embodiment of the present invention, the critical path delay based macro energy model creation process provides a base macro energy table and scaling functions (e.g., a bit width scaling function and a normalizing period scaling function). The scaleable power consumption estimation process utilizes the base macro energy table and scaling functions to estimate power consumption of a circuit. The base energy macro table comprises energy values that are based upon a critical path delay period and correspond to normalized toggle rates. Different bit width circuit toggle rates are converted to normalized toggle rates based upon time periods derived from a normalizing period scaling function. The normalized rates are utilized to lookup an energy per event value that is then scaled in accordance with a bit …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.