Controller arrangement for partial reconfiguration of a programmable logic device
US6810514B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2002 |
| Grant date | Oct 26, 2004 |
| Priority date | — |
| Expiry date | Sep 2, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for partial reconfiguration of a programmable logic device (PLD). In one embodiment, a configuration store is arranged for storage of configuration data for a selected subset of the reconfigurable resources of the PLD. A modification store is configured with addresses and associated data values. Each address in the modification store references an address in the configuration store, and each associated data value indicates a configuration state for one of the reconfigurable resources of the PLD. A controller is coupled to the configuration and modification stores and to the PLD. In response to a reconfiguration signal, the controller reads an address and associated data value from the modification store, updates the configuration store at the address read from the modification store with the associated data value, and downloads configuration data from the configuration store to the PLD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.