Method of reducing plasma charging damage during dielectric etch process for dual damascene interconnect structures
US6812145B2 · kind B2 · utility
Inventor
Key dates
| Filing date | Jun 5, 2003 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | Jun 10, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76844
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Charging damage, caused by electron shading during plasma etching in a dual damascene structure, is alleviated by first depositing a protective conductive layer which provides a conductive path for maintaining charge balance in the etched structures. This conductive layer reduces the buildup of unbalanced positive charge in the contact opening, and the damage done to underlying layers caused by the resultant tunneling current. Further, if the protective conductive layer comprises a material which can also serve as an interdiffusion barrier layer for the contact opening fill material, a separate subsequent step to deposit such a barrier layer on the contact opening sidewall is avoided. Further, in the process of doing lithography on the trench etch resist layer, the protective conductive layer also functions as an antireflective coating, permitting the stepper to accurately focus the desired pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.