Method of forming junction isolation to isolate active elements
US6812149B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2003 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | Sep 16, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/761
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming junction isolation to isolate active elements. A substrate having a plurality of active areas and an isolation area between active areas is provided. A first gate structure is formed on part of the substrate located in the active areas and, simultaneously, a second gate structure serving as a dummy gate structure is formed on the substrate located in the isolation area. A first doped region is formed in the substrate located at two sides of the first and the second gate structures. A bottom anti-reflection layer is formed on the substrate, the first gate structure and the second gate structure. Part of the bottom anti-reflection layer is etched to expose the second gate structure. The second gate structure is removed to expose the substrate. A second doped region serving as a junction isolation region is formed in the substrate located in the isolation area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.