Layer allocating apparatus for multi-layer circuit board
US6812409B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2002 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | May 16, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09663
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A layer allocating apparatus for a multi-layer circuit board is disclosed. In a preferred embodiment, the layer allocating apparatus arranged from top to bottom as a component layer, a ground layer, a power layer, and a solder layer. The powerlayer is sliced into a plurality of reference ground areas each is located at somewhere to correspond to signal layout areas of the solder layer, so as to allow signal lines of the component layer and solder layer to take reference to the reference ground areas on the adjacent power layer. The power layer also includes a plurality of power layers each provides different operating voltages, and electrically couples with corresponding power layouts of the solder layer and component layer through vias, thereby enlarging the total area of power planes, so as to provide a table power source and attenuate the ground/bounce effect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.