Dual interposer packaging for high density interconnect
US6812485B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2001 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | Feb 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K7/1061
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus that allows additional contact pads to be added to a package to support debug and test operations is disclosed. In a preferred embodiment, a circuit board apparatus includes a semiconductor package and an interposer for receiving the semiconductor package. The semiconductor package preferably includes a substrate having a matrix of conductive contact pads on both the top and bottom surfaces of the substrate. The interposer preferably includes a body having a matrix of interposer contact bumps on both the inner and outer surfaces of the body. Each interposer contact bump preferably includes a metal coating and is shaped to abut a contact pad of the semiconductor package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.