NAND flash memory and method of erasing, programming, and copy-back programming thereof
US6813184B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 10, 2003 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | Jan 10, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure is a NAND flash memory including a data loading circuit providing a program data bit into a page buffer having first and second latches. During a data loading operation for programming, the data loading circuit puts a pass data bit into a page buffer corresponding to a defective column, instead of a program data bit that is assigned to the defective column, responding to information of a column address involved in the defective column. It is available to provide a pass/fail check circuit for program-verifying without employing a fuse arrangement, making data of the defective column not affect a program-verifying result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.