Methods and apparatus for generating effective test code for out of order super scalar microprocessors
US6813702B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 1998 |
| Grant date | Nov 2, 2004 |
| Priority date | — |
| Expiry date | Jun 29, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/261
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for producing a test executable in a computer. The technique involves forming multiple instruction streams. The technique further involves dividing the multiple instruction streams into portions, and generating a combined instruction stream having the portions interleaved. Additionally, the technique involves creating a test executable from the combined instruction stream. The test executable can be used for testing a simulated processor in a computer. In particular, the test executable is loaded. Then, the test executable is run through the simulated processor to generate processor results and through a reference model to generate reference results. The processor results and the reference results are compared to determine whether the simulated processor operates correctly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.