Manufacturing method of CMOS devices
US6815279B2 · kind B2 · utility
19Cited by
7References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2001 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Jul 19, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device in which an NMOSFET and a PMOSFET are formed in a silicon substrate, wherein the gate electrodes of NMOSFET and PMOSFET are made of metallic materials, an Si—Ge layer is formed in at least part of the surface regions including the respective channel layers of the NMOSFET and PMOSFET, and the concentration of Ge in the channel layer of the NMOSFET is lower than the concentration of Ge in the channel layer of the PMOSFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.