Method for forming multi-layer metal line of semiconductor device
US6815334B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 30, 2002 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Dec 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a multi-layer metal line of a semiconductor device, including the steps of forming a first insulating film on a semiconductor substrate having a lower metal line thereon, planarizing the first insulating film until a predetermined thickness remains, removing the remaining portion of the first insulating film on the lower metal line, and forming an etch barrier layer on the entire surface. A second insulating film is formed with an oxide film thereon, and the oxide film, the second insulating film and the etch barrier layer are selectively etched to form a via contact hole exposing the lower metal line. The etching of the second insulating film is performed under specifies conditions so that a protective film is formed on a sidewall of the via contact hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.