Low resistance metal interconnect lines and a process for fabricating them
US6815342B1 · kind B1 · utility
3Cited by
11References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2001 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Mar 24, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Low resistance interconnect lines and methods for fabricating them are described herein. IC fabrication processes are used to create interconnect lines of Al and Cu layers. The Cu layer is thinner than in the known art, but in combination with the Al layer, the aggregate Cu/Al resistance is lowered to a point where it is comparable to that of a very thick Cu layer, without the additional cost and yield problems caused by using a thicker Cu deposition. Fuses for memory repair can also be fabricated using the methods taught by the present invention with only small variations in the process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.