Peter J. Wright
7Patents
4h-index
10Co-inventors
43Inventor score
Filing activity: Nov 27, 2001 → Jun 16, 2003
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6614283B1 | Voltage level shifter | Electricity | 25 | Expired |
| US6961915B2 | Design methodology for dummy lines | Electricity | 15 | Expired |
| US6566244B1 | Process for improving mechanical strength of layers of low k dielectric material | Electricity | 11 | Expired |
| US6617181B1 | Flip chip testing | Electricity | 9 | Expired |
| US6830984B2 | Thick traces from multiple damascene layers | Electricity | 4 | Expired |
| US6815342B1 | Low resistance metal interconnect lines and a process for fabricating them | Electricity | 3 | Expired |
| US6710453B2 | Integrated circuit containing redundant core and peripheral contacts | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.