Multi-layer film stack polish stop
US6815353B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2002 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Feb 5, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/26
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for improved dielectric polish control adjacent to device areas is described. This is particularly important for bipolar structures, although the method may be used for MOS structures as well. The method includes using highly selective methods for removing oxide layers and polish stop layers in a multi-layer film stack, providing an oxide edge step height that is substantially uniform regardless of the size of the adjacent device area. In one embodiment, the multi-film stack includes a first oxide layer, first nitride layer, second oxide layer, and second nitride layer. The multi-film stack is deposited on a substrate. Trenches are then etched through the multi-film stack and into corresponding regions of the substrate. A passivation oxidation layer is grown on the etched trench surfaces. The trenches are filled with oxide for isolating active device regions from one another. A first STI polish is performed, polishing the trench oxide to the level of the second nitride layer, which is then removed. The second oxide layer is then removed. A second STI polish is then performed, polishing the trench oxide to the level of the first nitride layer, which may then be removed. The…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.