Elimination of resist footing on tera hardmask
US6815367B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 3, 2002 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Apr 29, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/091
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process of eliminating resist footing on a hardmask when preparing a semiconductor wafer stack, comprising:a) depositing a layer of hardmask material on a substrate;b) subjecting the hardmask to oxygen under conditions sufficient to produce an oxide cap layer and provide a hardmask/oxide cap layer with a substrate reflectivity below 0.8%;c) forming a layer of SiO2 on the hardmask/oxide cap layer;d) forming a layer of photoresist on the layer of SiO2;e) patterning and developing the layer of photoresist by exposing photoresist; andf) etching exposed portions of the layer of hardmask/oxide cap layer/SiO2 layer to obtain a semiconductor wafer stack with no standing waves and free from resist footing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.