Single-poly EEPROM on a negatively biased substrate

US6815757B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Reed W. Adams · Mountain View, US
• William E. Grose · Dallas, US
• Sameer Pendharkar · Allen, US
• Roland Bucksch · Buch am Erlbach, DE

Key dates

• Filing date: Jan 22, 2003
• Grant date: Nov 9, 2004
• Expiry date: Jan 22, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/126

Abstract

Disclosed are devices and associated methods for manufacturing an EEPROM memory cell (10) for use on a negatively biased substrate (12). The invention may be practiced using standard semiconductor processing techniques. Devices and methods are disclosed for a floating gate transistor for use as an EEPROM cell (10) including a DNwell (14) formed on a P-type substrate (12) for isolating the EEPROM cell (10) from the underlying P-type substrate (12).