MOS transistor having reduced source/drain extension sheet resistance
US6815770B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2003 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Aug 14, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
Abstract
The present invention provides a novel MOS transistor structure. The MOS transistor includes a gate electrode formed on a semiconductor substrate, and a gate oxide layer formed between the gate electrode and the semiconductor substrate. A spacer is formed on each sidewall of the gate electrode. A lightly doped source/drain extension is formed under the spacer with a raised epitaxial layer interposed between the spacer and the semiconductor substrate. The epitaxial layer, which is part of the lightly doped source/drain extension, has a lattice constant that is greater than the lattice constant of silicon crystal. The epitaxial layer serves as a solubility enhancement layer that is capable of increasing active boron concentration, thereby reducing sheet resistance of the source/drain extension. A heavily doped source/drain region is formed in the semiconductor substrate next to the edge of the spacer. A raised silicide layer is formed on the heavily doped source/drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.