Flip-chip device with multi-layered underfill having graded coefficient of thermal expansion
US6815831B2 · kind B2 · utility
5Cited by
12References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 12, 2001 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Dec 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A die with flip chip bumps including at least one layer of filled underfill on the die surface and a layer of unfilled underfill over the filled underfill and the flip chip bumps. An IC assembly including a substrate with bumps and at least one layer of filled underfill on the substrate surface and a layer of unfilled underfill over the filled underfill and the bumps. A die or IC assembly with a plurality of filled underfill layers with differing CTE. Methods of making the dies and IC assemblies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.