Method for measuring NBTI degradation effects on integrated circuits
US6815970B2 · kind B2 · utility
32Cited by
6References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2002 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Aug 22, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/287
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of testing integrated circuits for the effect of NBTI degradation. A static DC stress voltage is applied to the voltage supply input of the circuit. This circuit is held at this voltage for a given stress period. The application of the DC voltage is equivalent to applying a negative gate bias, and isolates the effects of NBTI degradation from CHC (channel hot carrier) degradation or other degradation that occurs when the circuit has a clocked input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.