Scan cell systems and methods

US6815977B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Anil K. Sabbavarapu · Austin, US
• Talal K. Jaber · Austin, US
• Grant McFarland · Portland, US
• Paven R. Sunkerneni · San Jose, US
• David M. Wu · Austin, US

Key dates

• Filing date: Dec 23, 2002
• Grant date: Nov 9, 2004
• Expiry date: Apr 28, 2023

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318552
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

According to some embodiments, a circuit includes a Domino state element, a master latch to receive a first clock signal and to store a value in the Domino state element in response to the first clock signal, and a slave latch to receive a second clock signal and to output the value in response to the second clock signal. Some embodiments provide a first state element coupled to a first node, a master latch coupled to the first state element, the master latch to receive a first storage signal, a first load signal, a first clock signal and a first scan value signal, a second state element coupled to a second node, the second node sequential to the first node, and a slave latch coupled to the second state element, the slave latch to receive a second storage signal, a second load signal, a second clock signal and a second scan value signal.