Design-for-test technique for a delay locked loop
US6815986B2 · kind B2 · utility
14Cited by
10References
21Claims
0Family size
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Key dates
| Filing date | Jul 16, 2002 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Jan 2, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop implementing design-for-test features to test for, among other, stuck-at-faults is provided. The delay locked loop uses multiplexers as design-for-test devices for controllability purposes and flip-flops as design-for-test devices for observability purposes. Such implementation of design-for-test features within a delay locked loop allows for pre-packaging delay locked loop verification and testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.