Clock frequency multiplier
US6815991B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2003 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Jan 9, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock frequency multiplier design is provided. The clock frequency multiplier includes an input stage arranged to receive an input clock signal, a first clock cycle generator stage operatively connected to the input stage and arranged to generate a low pulse on a first signal dependent on a low phase of the input clock signal, a second clock cycle generator stage operatively connected to the input stage and arranged to generate a low pulse on a second signal dependent on a high phase of the input clock signal, and an output stage operatively connected to the first clock cycle generator stage and the second clock cycle generator stage and arranged to output a high pulse on an output clock signal for every low pulse on the first signal and the second signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.