Apparatus for detecting multiple hits in a CAMRAM memory array
US6816396B2 · kind B2 · utility
6Cited by
9References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2003 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Apr 1, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CAMRAM capable of detecting multiple hit is disclosed. The CAMRAM includes a random address memory, a content-addressable memory, a set of index address lines and a set of multiple-hit detection address lines. The index address lines and the multiple-hit detection address lines are complementarily connected to a set of matchlines via transistors. Coupled to the index address lines and the multiple-hit detection address lines, a comparator circuit is capable of outputting a multi-hit signal when more than one of the matchlines are turned on simultaneously during an address comparison operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.