Bi-directional read write data structure and method for memory
US6816397B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2003 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | May 29, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
As disclosed herein, an integrated circuit memory is provided which includes primary sense amplifiers coupled for access to a multiplicity of storage cells, second sense amplifiers, and pairs of input/output data lines (IODLs), each IODL pair being coupled to a primary sense amplifier, and each IODL pair carrying complementary signals representing a storage bit. The memory further includes pairs of bi-directional primary data lines (BPDLs), each BPDL pair being coupled to a second sense amplifier and each BPDL pair being adapted to carry other complementary signals representing a storage bit. Local buffers are adapted to transfer, in accordance with control input, the complementary signals carried by the IODLs to the BPDLs, and vice versa.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.