Non-volatile semiconductor storage device composed of NAND type EEPROM and deletion verification method in non-volatile semiconductor storage device
US6816411B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2003 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Jul 1, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND column has memory cell transistors connected in series by a current passage. Word line drive circuits supply a low voltage to a word lines. A potential supply circuit supplies a high potential higher than the low potential, to a semiconductor region in which the memory cell transistors are formed, to delete contents stored in the memory cell transistors. In deletion verification which verifies that the contents stored in the memory cell transistors have been deleted, a read is executed on each of the word lines. In the read, the word line drive circuit provides the selected one of the word lines with a determination potential used to determine whether or not the contents have been deleted, while providing the other non-selected word lines with a read potential higher than the determination potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.