Resequencing packets at output ports without errors using packet timestamps and timestamp floors
US6816492B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2000 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Sep 26, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/552
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are disclosed for propagating timestamp floors throughout a packet switching system and using the timestamp floors received at a first component of the packet switching system to determine when a packet may be sent from a packet switching system. Each input of a first stage of a packet switching system maintains a floor register which is updated by copying the timestamp from each arriving packet. In some systems, if a packet is not received during a packet time, the timestamp is automatically updated, typically by adding a fixed time value. Periodically, the first stage switching element forwards a timestamp floor to the next stage switching elements. In one implementation, this distributed timestamp floor is the lesser of the earliest timestamp in one of the floor registers in the input queues, and the earliest timestamp in an output queue for the particular next stage switching element. In a buffering component, typically an output interface or possibly a final stage switching element, each output queue maintains a floor register for that output. When a packet in the particular output queue has a timestamp less than or equal to the timestamp floor maintained…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.