Bus precharge during a phase of a clock signal to eliminate idle clock cycle
US6816932B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2001 |
| Grant date | Nov 9, 2004 |
| Priority date | — |
| Expiry date | Dec 31, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4077
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a bus and a circuit for precharging the bus. The circuit may be coupled to receive a clock signal associated with the bus, and may be configured to precharge a bus during an interval of the period of the clock signal, the interval being between a first edge (rising or falling) and the subsequent edge (falling or rising). A second interval within the period and excluding the interval may be used to perform a bus transfer. In this manner, both precharging and transfer may be performed in the same clock cycle. Bandwidth of the bus may be improved since transfers may occur each clock cycle, rather than having a non-transfer clock cycle for precharging.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.