Method for fabricating semiconductor device with loop line pattern structure
US6818515B1 · kind B1 · utility
24Cited by
5References
2Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 23, 2003 |
| Grant date | Nov 16, 2004 |
| Priority date | — |
| Expiry date | Jun 23, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An alternating phase shift mask with dark loops thereon, a memory array fabricated with the alternating phase shift mask, and a method of fabricating the memory. The dark loops in the mask always separate first regions with 180° phase difference from second regions with 0° phase difference to define active areas or gate-lines in a DRAM chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.